mritunjay bihari singh

Hardware Verification Architect | UVM | RTL Debugging | Freelance Consulting Shipping verified chips since 2014. Let's talk about your verification challenges.

Joined on Jul 24, 2026

Jul 27

Before your DV team writes a single testbench line, make sure you have these 7 things. (Most teams skip at least 3.)

1 min read

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mritunjay bihari singh

Jul 27

I once found a silicon bug in a protocol spec — not in the RTL.

#architecture #hardware #testing

1 min read

mritunjay bihari singh

Jul 27

Most UVM testbenches fail coverage closure for one reason nobody talks about — and it's not your constraints.

1 min read

mritunjay bihari singh

Jul 24

5 UVM Patterns Every Verification Engineer Should Know

#architecture #softwareengineering #systemdesign #testing

2 min read

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mritunjay bihari singh

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Before your DV team writes a single testbench line, make sure you have these 7 things. (Most teams skip at least 3.)

Want to connect with mritunjay bihari singh?

I once found a silicon bug in a protocol spec — not in the RTL.

Most UVM testbenches fail coverage closure for one reason nobody talks about — and it's not your constraints.

5 UVM Patterns Every Verification Engineer Should Know